Power Switch and MCU GPIO current leakage | ๐Ÿงจ Engineering Schematic Solutions


If you have battery powered device all peripheral chips (ICs) could be connected to the power switch (IC or transistor) to have ability to fully disable powering of the peripherals in standby (save) mode.ย 

Issue Description

Most of switches in case of EN=0 (disabled state) pulls output to the ground to discharge capacitors and prevent charge accumulation.


In this case high output signal from MCU (e.g. MOSI โ€” Master Output Slave Input) cause very high current leakage through internal ESD protection diode (D1) to the ground.



To prevent any current leakage all pins connected to the unpowered chip should have LOW output state or reconfigured as FLOAT (high impedance).

  1. DisableRailPower(){
  2. /* Force make pins LOW */
  3. digitalWrite(CS, LOW);
  4. digitalWrite(MOSI, LOW);
  6. /* Then disable power of the chip */
  7. digitalWrite(POWER_BUS_EN, LOW);
  8. }

So, in MCU deep sleep pins automatically became float, but in active state is should be forced done in code before actual rail power disabling.


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If you use just P-FET as switch element that's not actual, because you have disabled state as float (not connected to anything):


Also, some of voltage regulators can have float output in disabled state (EN=0), but it's not always clearly specified in the datasheets.

But most of LDO with controlled output (separate EN=Enable, CE=Chip Enable) pins will have two states:


Most of switch IC specially designed for power control will have also two states. Sometimes LOW state means connection resistor with moderate resistor (~230 Ohm) to make discharging more smooth, which is called Quick-Output Discharge (QOD)

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