π§§ Using net ties in schematic and board (PCB design process improvements)
Intro
If you design schematic consider using net ties, which can help during board tracing.
Net Tie
It's copper polygon, that divide one physical connection (one net) to the 2 or moreΒ nets with different names.
| GND (Ground) -> | DGND (Digital Ground) |
| AGND (Analog Ground) |
Symbols
Default KiCad library contain several symbols for net ties with different net quantities.
Footprints
KiCad library also provides several footprints with different types (SMD/THT), sizes and net quantities:
Schematic
The most basic and widespread example is correct tracing current measurement shunt.Β In this case the high current must flow through current measurement resistor and the voltage drop should be measured directly from shunt, so the measurement tracks should be connected directly to the resistor pads to eliminate measuring losses at tracks.
Also it will be useful for ADC with differential input.
Layout
Now you can clearly see how to name properly connection:
Special Component with Four pins
Another comprehensive technique is to use special symbol and footprint for current sensing resistors (shunts). The symbol can have separate pins for pass and measuring:
So the schematic is clear and connection on board also will be 100% correct. See RS2201 as example from standard KiCad library:
So the schematic is clear and connection on board also will be 100% correct:
Especially this required for specially designer shunts with separate pins for pass current and measurement pins.
KiCad Rule Issues
Footprint
To have clear DRC be sure, that special footprint have net tie exclusions (allowing to short different nets) in Footprint Properties:
Zones
In some cases (connection between polygons and net tie) can causes DRC clearance error, so this rule exception resolve possible violation:
# Rule for Net Ties (rule "ALL NET TIES AND OTHER POLYGONS" (condition "A.Type == 'Graphic' && B.Type == 'Zone'") )
Conclusions
| π’ | Using net ties is a good practice to guarantee correct connection on the board and a clear schematic diagram |
| π΄ | Check production files with net ties since manufacturers (like JLCPCB) can kill net ties because their software thinks it's shortcut between different nets. Tip: extend center copper region to pads |
- Comments



